Address allocation of Omron PLC - CPU unit address allocation

Create Date: 2024-8-30 12:03:23|Source: Omron/Omron

1. CPU unit address allocation

Type X and XA CPUs

The X and XA CPU units come with 40 I/O, of which 24 are inputs and 16 are outputs, and the input part of the CIO area occupies 0 - 1 channel, with a total of 24 input bits:

12 of the bits are bits 00 of the 0 channel - bits 11;

The other 12 bits are bits 00 - bits 11 of the 1st channel;

Bit 12 – bit 15 – that is not used in channels 0 and 1 – will always be cleared and cannot be used as an internal auxiliary working bit.

The output of the X and XA CPU units is 16 points, and the output section of the CIO area occupies 100-101 channels, and a total of 16 output bits are allocated:

8 of the bits are bits 00 - bits 07 of the 100 channel;

The other 8 bits are bits 00 - bits 07 of channel 101;

Bit 08 – bit 15 in channels 100 and 101 can be used as internal auxiliary stations.

The CP1H-XA CPU comes with analog input and output, of which 4 analog inputs occupy 200-203 channels, and 2-channel analog outputs occupy 210-211 channels.

Y-type CPU

The CP1H-Y CPU comes with 20 I/O, including 12 input points and 8 output points.

Therefore, the input of the Y-type CPU unit occupies a total of 12 points of channel 0 and channel 1 in the CIO area;

Bit 12 – bit 15 – that is not used in channels 0 and 1 – will always be cleared and cannot be used as an internal auxiliary working bit.

The output of the Y-type CPU unit is 8 points, which is also due to the occupation of the special terminal for pulse input and output:

The output of the CPU unit occupies a total of 8 points of 100 channels and 101 channels in the CIO area;

Bit 08 – bit 15, which is not used in channels 100 and 101, can be used as an internal auxiliary working station.
Address allocation of Omron PLC - CPU unit address allocation

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